Semiconductor integrated circuit structure



K. E. BEAN ETAL SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE OriginalFiled Sept. 4. 1964 Oct. 13, 1970 3 Sheets-Sheet 1 (RESISTOR/l8(EM/TTER)24 (PH/5 23 if, m 4

, INVENTORS KENNETH E. BEAN WALTER R. RUN YAN @Ct. 13, 1970 BEAN ETAL3,534,236

SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE Original Filed Sept. 4. 19643 Sheets-Sheet 2 INVENTOR KENNETH E. BEAN WALTER R. RUNYAN 0. V" JATTORNEY Oct. 13, 1970 N ETAL 3,534,236

SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE Original Filed Sept. 4. 19643 Sheets-Sheet 3 I I NV ENTOR KENNE 7"H E. BEA/V WAL 75/? 'P. RUN m N bI ATTORNEY United States Patent 3,534,236 SEMICONDUCTOR INTEGRATEDCIRCUIT STRUCTURE Kenneth E. Bean, Richardson, and Walter R. Runyan,

Dallas, Tex., assignors to Texas Instruments Incorporated, Dallas, Tex.,a corporation of Delaware Original application Sept. 4, 1964, Ser. No.394,408, now Patent No. 3,379,584, dated Apr. 23, 1968. Divided and thisapplication Nov. 24, I967, Ser. No. 707,901

Int. Cl. H01] 19/00 US. Cl. 317235 1 Claim ABSTRACT OF THE DISCLOSURE Amonolithic integrated circuit structure is provided comprising first andsecond monocrystalline epitaxial semiconductor layers of a firstconductivity type on a monocrystalline substrate of oppositeconductivity type. Electrically isolated device regions are provided bya deep diffusion pattern extending through both epitaxial layers andhaving the same conductivity type as the substrate. A suitable techniquefor the fabrication of the structure of the invention includes the stepof depositing the first epitaxial layer on a substrate surfacecrystallographically oriented at a small angle from the (111) plane.

The application is a division of application Ser. No. 394,408, filedSept. 4, 1964, now US. Pat. No. 3,379,584.

This invention relates to a semiconductor integrated circuit structure,and more particularly to a doubleepitaxial layered semiconductorstructure in which electrically isolated regions are provided by a deepdiffusion pattern extending through the epitaxial layers.

The technique of epitaxial deposition, whereby overlying layers may begrown on a crystalline substrate, is known in the art. By such epitaxialtechnique (epitaxy), like material is joined to a substrate to form aproduct that is essentially monocrystalline in nature. Epitaxy makes itpossible to produce many devices which may not be produced in quality byother techniques. Moreover, in certain cases epitaxy offers a much morereliable and inexpensive technique for production of high qualitydevices than may be obtained by other known techniques of fabrication.

It is desirable to provide a device having more than one epitaxial layerin some instances. However, in the prior art, the proper alignment ofvarious necessary regions, zones or structures within the device haspresented a problem.

An object of the present invention is to provide a technique for theprecise formation at desired locations of various regions, zones orstructures in successive layers of a wafer in which a semiconductordevice is formed; for example, the precise formation of various zones orregions in the substrate and in one or more successive layers overlyingthe substrate. A further object is to provide a method of forming awafer in which an epitaxial layer with a desired visible pattern isproduced. Yet another object is to provide a method for producing asemiconductor integrated circuit having successive epitaxial layers withaligned regions therein and in the substrate. It is an additional objectto provide means for growing an epitaxial layer at lower temperaturesand/ or on substrates of poorer quality than is ordinarily possible.

In accordance with the present invention, a process is provided formaking a monocrystalline wafer. This process comprises the steps ofpreparing a monocrystalline substrate with a face thereon cut at leastabout 0.5 and no greater than about with the (111) plane and "iceepiaxially depositing a layer of material on the face of the substrate.

In a more specific aspect the process comprises making a monocrystallinewafer by preparing a monocrystalline substrate with a face thereon cutat least about 0.5 and no greater than on the order of about 10 with the(111) plane; forming a visible pattern in the surface of the face of thesubstrate; epitaxially depositing a layer of material on the face overthe pattern; and positioning structure over the epitaXially-depositedlayer in a substantially precise location with respect to the pattern.It should be noted that the epitaxially-deposited layer maintains theintegrity and visibility of the pattern originally formed in the surfaceof the face of the substrate. It is preferred that the angle at whichthe face is cut between about 1 and 3 with the (111) plane. It isfurther preferred that the monocrystalline substrate be silicon, butother semiconductor materials, preferably those of cubic crystalstructure, may be effectively used, e.g. germanium, gallium arsenide,and indium antimonide.

In a specific preferred embodiment of the present invention, the processfurther comprises forming diffusion regions in the initial epitaxiallayer in substantially precise locations with respect to the visiblepattern. Thereafter, the steps may be repeated to form an additionalepitaxial layer, or layers, having diffusion regions in substantiallyprecise locations with respect to the visible pattern.

In accordance with the structural aspects of the present invention, amonocrystalline wafer for a solid integrated network is provided. Thewafer includes a substrate of substantially monocrystallinesemiconductor materials, a first substantially monocrystalline epitaxiallayer overlying the substrate, a second substantially monocrystallinelayer overlying the first epitaxial layer, and a deep diffusion regionrunning through the first and second epitaxial layers and into thesubstrate.

In a specific preferred embodiment, the structure referred to in theforegoing paragraph is such that the deep diffusion region is configuredto provide isolation zones adjacent the surface of the wafer. Thesubstrate is of a P- conductivity type material, the first epitaxiallayer of an N+ type material, the second epitaxial layer of the Nconductivity-type, and the deep diffusion region of heavily doped P+conductivity type. Further, a pair of NPN tra'nsistors and a pair ofresistors are formed in the isolation zones. These elements are disposedto define a solid NOR logic network.

For a more complete understanding of the present invention and forfurther objects and advantages thereof, reference may now be had to thefollowing description taken in conjunction with the accompanyingdrawings in which:

FIG. 1 is a pictorial view in section of a semiconductor integratedcircuit of the double epitaxy type which may be fabricated in accordancewith the principles of this invention;

FIG. 2 is a schematic diagram of the NOR logic circuit embodied in thedevice of FIG. 1;

FIG. 3 is an elevational view in section taken along the lines 3-3 inFIG. 1.

FIGS. 4 through 10 are schematic sectional views in elevationillustrating sequential steps in forming a wafer having a singleepitaxial layer overlying a substrate with a single simple diffusionregion in it;

FIG. 11 is an analogous view to FIG. 10 and illustrates structure formedby the same steps as used in forming the structure of FIG. 10, exceptthat the substrate face is prepared to lie a a critical angle with the(111) plane, in accordance with the present invention;

FIG. 12 is a schematic view illustrating a method of preparation of asubstrate having a face inclined at a critical angle with the (111)plane;

FIGS. 13, 14, 16, 17, 19 and 21-23 are sequential pictorial views insection, illustrating the steps of preparation of the structure of FIG.1; and

FIGS. 15, 18 and 20 are partial sectional elevational views taken along15-15, 18-18 and '2020 of FIGS. 14, 17 and 19, respectively.

With reference to FIG. 1, there is shown a semiconductor integratedcircuit which is made in accordance with the epitaxial techniques ofthis invention. This integrated circuit includes a chip or wafer ofsingle crystal semiconductor materal, typically silicon, with the wafercomprising a P conductivity-type substrate 11 upon which there is growna first N+ epitaxial layer 12 and a second N conductivity-type epitaxiallayer 13. Overlying the top layer 13 is a coating 14 of silicon dioxidewhich is formed during the final ditfuson operatons. A pattern or gridof heavily-doped P conductivity-type isolation regions 15 extend throughthe N conductivity-type epitaxial layers 12 and 13 into the substrate 11to create isolated zones of N conductivity-type semiconductor materialadjacent the top surface of the Wafer 10. In these isolated Nconductivity-type zones are formed the active and passive circuitelements which provide the integrated circuit. In the device of FIG. 1,which embodied the NOR logic circuit of FIG. 2, the central region hasformed therein a pair of NPN transistors 16 and 17 which have a commoncollector region 22. Also, a pair of resistors 18 and 19 are provided byelongated diffused P conductivity-type regions 20 and 21, respectively,formed in the N conductivity-type layer 13. The transistor 17 includes acollector region 22 which is part of the lightly-dopedN-conductivity-type epitaxial material of the layer 13, and furtherincludes a planar-diffused P conductivity-type base region 23, and an Nconductivity-type planar-diffused emitter region 24. These base andemitter regions are formed by well-known diffusion techniques includingforming an oxide coating, using photoresist operations for selectiveremoval of the oxide, diffusion from an impurity-entrained vapor whilecreating another layer of oxide, followed by repetition of these stepsas necessary. It should be noted that the resistors 18 and 19 arecreated by the same P conductivetype diffusion operation which forms thebase 23. The transistor 16 is exactly like the transistor 17, which maybe seen in section. Connection to the common collector region 22 for thetwo transistors is provided by an elongated metal contact 26 which isdeposited in a hole etched in the oxide layer 14. Deposited metal 27extending from the contact 26 over the oxide 14 makes a connection toone end of the resistor 18 while a further extension of the depositedmetal 27 forms a land 28 on top of the oxide 14 to facilitate making aconnection to the output of the circuit. Another conductiveinterconnection 29, seen in FIG. 3, overlies the oxide 14 but extendstherethrough to the emitters of each of the transistors 16 and 17 sothat these emitters are electrically connected together and alsoconnected to a land 30 which provides the negative bias terminal for theintegrated circuit. A base contact 31 on the base 23 of the transistor17 is connected by a deposited metal strip 32 overlying the oxide 14 tothe end of a resistor 33 (not shown except in FIG. 2), with the otherend of this resistor being connected to a land which provides one of theinput terminals to the integrated circuit. The base of the transistor 16is connected in a similar manner by deposited metal 34 to one end of theresistor 19 while the other end of this resistor is connected by adeposited metal strip 35 to a land 36 which provides the other input tothis gate circuit.

The semiconductor integrated circuit described thus far makes use ofseveral features which require the fabrication procedure of thisinvention as will be described hereinafter. One of these features is theheavily-doped buried N+ region 12. This buried highly-conductiveepitaxial layer 12 is needed to facilitate making low re i ance con.-

nection to the collector region of the transistors. The actual operatingcollector region of the transistor should be of lightly-doped, highresistance N conductivity-type material so that the switching speed ofthe transistor is high and the back breakdown voltage of thecollector-base junction is also high. This condition, however, makes theresistance from the collecting region of the transistor, i.e. thatresistance immediately underlying the part of the base 23 which isunderneath the emitter 24, to the collector contact 26 high unless someprovision is made. If this resistance is high, it means that thecollector saturation resistance of the transistor in the circuit isundesirably high. The resistance from the collecting region of thetransistors to the collector contact 26 is lowered by means of the lowresistance, heavily-doped epitaxial N-I- conductivity-type region 12which is in parallel electrically with the high resistanceN-conductivity-type region 22. It should be noted that the verticaldimension of the FIG. 1 is greatly exaggerated so that in reality thedistance from the contact 26 to the heavily-doped layer 12 is very, verysmall compared to the distance from the contact 26 to the collectingregion. Another feature which the integrated circuit described aboveutilizes is the isolation regions 1'5 formed by a plurality of diffusionoperations performed before the top epitaxial region is grown. Thistechnique avoids the necessity of prolonged diffusion operations such aswould be necessary if an attempt was made to create the entire regions15 by a single diffusion from the top surface after all of the epitaxialregions had been grown. In the latter case, it would be very difiicultto convert the heavily-doped N-+ region 12 to P conductivitytype andalso the lateral extension of the isolation diffusion regions might beexcessive. It is for these reasons that the isolation diffusions areperformed early in the process, one or more of these diffusions beingburied underneath the epitaxial layers.

To appreciate the criticality of the precise alignment necessary formaking the successive isolation diifusions, the extreme small size ofthe device described above should be noted. The chip 10 may itself beonly perhaps 30 or 40 mils square, meaning that it would be barelydiscernible to the naked eye at arms length. The width of the isolationregions .15 may be only one or two mils, meaning that a very slightmisalignment of the mask for the successive diffusion operations, makingthe diffusions fail to overlap, would result in the device beinguseless. Actually the chip 10 is cut from a slice of single crystalsilicon which would be perhaps one inch in diameter. A large number ofthe integrated circuits of FIG. 1 would be formed simultaneously on aslice, perhaps 50 to of these circuits being formed at one time, afterwhich the slice would be scribed and broken into individual integratedcircuits as seen in FIG. 1.

To facilitate an understanding of the present invention and the problemsolved by it, the preparation of a uni tary monocrystalline multilayerwafer of silicon having a simple single diffusion region therein willnow be described. The preparation is sequentially illustrated in FIGS. 4through 10.

Referring to FIG. 4, a substrate 41 (e.g. a slice of substantiallymonocrystalline silicon) has a thin layer 43 of silicon dioxide on itsupper surface. This layer 43 is formed, for example, by depositing thesilicon dioxide on the surface of the layer through reaction of silicontetrachloride gas and carbon dioxide at a temperature of about 1200 C.for a reaction period of on the order of about five minutes.Alternatively, the surface portion of the substrate may be thermallyoxidized by passing steam and oxygen over it in a reactor at about 1200C. for a suitable period until an oxidation layer of desired thicknessforms. The thickness of the silicon dioxide layer 43 may vary, buttypically it is on the order of about 10,000 angstroms.

The silicon dioxide layer 43 of substrate 41 next has a thinphotosensitive film 44 of a photoresist solution applied to its uppersurface. The precise chemical formula of this solution is not availableto the public, but the solution may be obtained from Eastman KodakCompany under the designation KMER (Kodak Metal Etch Resist).Ultraviolet light is then selectively conducted to the top of the thinfilm 44 to expose preselected regions in accordance with a desiredpattern. For example, a glass mask having blacked-out areas thereon, sothat light is transmitted only through the desired pattern, may be usedto cover the film 44 while ultra-violet light is impinged on the glassmask. It will be apparent that exposed and non-exposed regions willresult in the photoresistant film 44. FIG. 5 schematically illustratesthe resulting appearance of the in-process work at this time, with thefilm 44 having exposed regions 44b and the non-expected region 44. Theboundary between these regions is indicated schematically in FIG. 5 bydottde lines.

The structure of FIG. 5 is next treated with non-exposed photoresistsolvent (a light chloronated hydrocarban solvent, e.g. trichloroethyleneand others available through Eastman Kodak Company). The appearance ofthe in-process work after treatment with the non-exposed photoresistsolvent is shown in FIG. 6, wherein it will be seen that the non-exposedregion 44a of film 44 has been removed. Note that silicon dioxide layer43 is bared in the area on which the removed non-exposed film region 44apreviously rested.

The work product from FIG. 6 is next etched with a concentrated solutionof hydrofluoric acid, as is wellknown in the art, to remove the silicondioxide layer in the area in which it is not protected by the exposedphotoresist film 44b. The appearance of the in-process work after theetch step of FIG. 6 is illustrated in FIG. 7 wherein it will be notedthat a central channel is defined which has as its bottom the surfacearea 45 of the silicon substrate 41 which was bared by the etch removalof silicon dioxide film.

Thereafter, exposed photoresist solvent (for example, a hot mixture ofsulfuric acid and nitric acid) is used to remove the exposed photoresistfilm regions 44b. The in-process work is deposited in a furnace and adopant (for example, boron) is deposited on the exposed upper surface ofsilicon substrate 4.1 and thereafter diffused into the silicon to definethe diffused region 46. The boron deposition and diffusion step may beconducted by depositing the boron from boron tetrabromide and oxygen atabout 1000 C., followed by a diffusion step at a temperature of about1200 C., preferably conducted in dry oxygen for several hours.

At this point, the in-process work appears as is illustrated in FIG. 8,which illustrates the diffused region 46. Attention is directed to thechannel or depression 47, with its sides or shoulders 48, which define asharp visible pattern on the upper face of the silicon substrate 41.This pattern results from a change in the level of the silicon surfaceresulting from oxidation during the diffusion step. Accordingly, a verythin layer of silicon dioxide (omitted from FIG. 7, and other analogousfigures herein, for clarity) overlies the pattern so produced. This thinlayer is removed along with the silicon dioxide layer 43 by immersingthe product so illustrated in FIG. 8 in hydrofiuoric acid solution. Theappearance of the resulting product is illustrated in FIG. 9.

The product of FIG. 9 is now ready for the deposition of additionalmonocrystalline silicon on its upper surface. For example, with thediffusion region 46 being of the P+ type, the epitaxial deposition mightbe conducted to apply an N+ heavily-doped silicon layer from silicontetrachloride and hydrogen gases carrying a small quantity of antimonytetrachloride or other suitable N- conductivity type dopant. Suchepitaxial deposition may be conducted at an elevated temperature, forexample, about 1250 C. Various techniques of epitaxial deposition may beemployed, including those explained in Epitaxial Silicon Films byHydrogen Reduction of 6 SiCl Theuerer, Electrochemical Society, vol.108, pp. 649-653, (1961), and in US. Pat. No. 2,692,839 (referringspecifically to germanium, but also applicable to silicon at highertemperatures).

FIG. 10 is a partial sectional view illustrating the portion ofsubstrate 41 which carries the diffusion region 46 and an immediatelyoverlying epitaxially-deposited layer 49. Note that a depression orchannel 50, having side or shoulder portions 51, is present on the uppersurface of the epitaxially-deposited layer 49. The shoulders 51 ofchannel 50, as illustrated in FIG. 10, slope substantially and do notprovide a well-defined indication of the precise location of theunderlying diffusion region 46. The pattern on the upper surface of theepitaxial layer 49 is thus not sharp and is not generally reliable as ameans of locating the diffusion region 46 for subsequent operations.Accordingly, great difficulty is presented if it is desired to locate anadditional mask and perform subsequent diffusions precisely located withrespect to region 46.

In accordance with the present invention, the problem illustrated inFIG. 10 and discussed in the preceding paragraph is solved by an initialpreparation step in which a silicon substrate is prepared by cutting itsupper face 53 at a small angle, ranging from no less than about 0.5 tono more than about 10 with the (111) plane [the designation 111) beingthe Miller indices, as is known in the art]. Referring to FIG. 12, aportion of an elongated crystal grown along the (111) plane isillustrated as 55. For preparation of slices suitable for practice ofthe present invention, substrates are formed from the crystal by cuttingalong a plane at a small angle 0 with the (111) plane. The angle 0ranges from about 0.5 to the order of about 10, preferably from about 1to 3.

Accordingly, crystal substrates are produced which have faces such as 53inclined at the angle 0 with the (111) plane. The trace of the cuttingplane is illustrated in FIG. 12, along the dotted line designated A, andthe trace of the (111) plane is shown along the dotted line B. The anglebetween them is exaggerated in FIG. 12 for clarity of illustration.Successive slices may be cut from crystal 55 along spaced apart planessuch as A and A", which are parallel to the face 53.

Referring to FIG. 11, the substrate 41' is analogous to substrate 41(FIGS. 4-10) except that its upper face 53 is at a small angle, e.g.about 1.5", with the (111) plane. The substrate 41 has had all of theoperations performed on it that were performed on substrate 41 at thestate illustrated in FIG. 10. However, a material difference can be seenbetween the structures of FIG. 10 and FIG. 11. The shoulders 51' in theepitaxial layer 49 of FIG. 11 are sharp, contrasted to the slopingshoulders 51 in the epitaxial layer 49 of FIG. 10. These sharp shoulders51 rather precisely overlie the shoulders 48 in the substrate 41.Consequently, a quite sharp pattern is produced on the upper surface ofepitaxial layer 49'. The presence of this sharp pattern makes itpossible to quite precisely locate, with respect to diffusion region 46'in substrate 41', a mask or other desired item for subsequent processingor treatment. For example, an additional diffusion region may now beformed in epitaxial layer 49' by the same techniques with which region46 was formed in silicon wafer 41. Such a diffusion region may be madeto overlie diffusion region 46, if desired. In the alternative,diffusion regions may be formed at locations spaced at desiredpredetermined distances from diffusion region 46. If a diffusion regionis formed which directly overlies the diffusion region 46', furtherdiffusion may be accomplished to cause the diffusion regions initiallypresent to merge with it, if desired. Further detail on this procedurewill be explained at a later point hereinafter.

The making of a semiconductor integrated circuit of the double-epitaxytype having the structure previously described in connection with theFIGS. 1-3, will now be explained. The various operations will besummarized briefly in view of their direct analogy to the operationexplained above in connection with FIGS. 1 through 12.

FIG. 13 illustrates the P-conductivity-type silicon substrate 11 withits upper surface or face cut at a small angle from the (111) plane, forexample, 2. Preparation of the substrate 11 may be accomplished, forexample, by cutting the substrate from an elongated silicon crystalwhich was grown on the (111) plane. Such cutting takes place along aplane misaligned 2 from the (111) plane. The cutting operation may beaccomplished by various means, for example, by cutting with a diamondsaw positioned rather precisely along the desired cutting plane whilethe (111) grown crystal is firmly supported. The face ofP-conductivity-type substrate 11 is covered by the silicon dioxide layer61. The silicon dioxide layer '61 is channeled to expose preselectedupper areas of the face of substrate 11. The technique of forming theoxide layer and selectively removing desired portions of it waspreviously described herein in connection with FIGS. 4-8.

Heavily-doped P-conductivity-type diffusion regions 15a are next formedin the product of FIG. 13. The diffusion technique described inconnection with FIG. 8 may be employed for this purpose. The resultingproduce is illustrated in FIG. 14. FIG. 15 is a partial section showingan enlarged view, including a diffusion region 15a, illustrating theshoulders 63 which overlie and define the opposite sides of theillustrated diffusion region 15a.

FIG. 16 illustrates the appearance of the product of FIG. 14 after theoxide layer 61 is removed, e.g. with hydrofluoric acid. Thereafter, anN+ epitaxial layer is deposited in the manner described in connectionwith FIG. 11, eg by deposition of silicon from a mixture of silicontetrachloride and hydrogen gases containing heavy dopant quantities ofantimony pentachloride therein. The resulting epitaxial layer 12 (FIG.17) has a sharp pattern on its face. This pattern is clearly defined bythe sharp shoulders 65, which substantially directly overlie shoulders63 on the substrate 11 (see the partial sectional view of FIG. 18).

Thereafter, the process of forming an oxide film, selectively removingdesired portions of it, and diffusing impurities into the expitaxiallayer 12 is repeated to form P conductivity-type regions 15b whichdirectly overlie the P conductivity-type regions 15a in substrate 12(FIGS. 19 and 20). Note that the precise alignment necessary for formingregion 15b over 15a was made possible by the sharp, visible pattern onthe oxide layer 67 which Was formed on top of the epitaxial layer 12.This oxide layer retains the integrity of the sharp pattern of theepitaxial layer 12 on which it is formed. Accordingly, shoulders in theoxide layer directly overlying the shoulders 65 in the epitaxial layer12 provide the pattern by which to align the mask on a film ofphotoresist applied over the oxide. In this connection, bear in mindthat the photo-resist film is transparent and, accordingly, visualalignment is possible. Thus, the glass mask previously used to preparethe pattern for diffusion regions 15a is again used, this time preciselyvisually alinged to lie directly over the diffusion regions 15a. Afterexposure to ultraviolet light, removal of non-exposed photo-resist, andetching, boron diffusion is repeated. The resulting product, withdiffusion regions 15b lying directly above diffusion regions 15a, isillustrated in FIGS. 19 and 20. FIG. 21 illustrates the resultingproduct after removal of the oxide layer 67.

Referring to FIG. 22, an additional epitaxial layer 13, having diffusionregions 15c precisely aligned to lie directly over diffusion regions 15aand 15b, is illustrated. The same technique used in connection withpreparation of epitaxial layer 12 and diffusion regions 15b is used toprepare this epitaxial layer 13 with its diffusion regions 150. Notethat the alignment was made possible by the retention of the sharppattern on the face of he second epitaxial layer (i.e. layer 13). Anoxide coating 69 overlies the second epitaxial layer 13. This oxidelayer is formed by the techniques previously described.

The structure of FIG. 22 is thus seen to comprise the precisely alignedoverlying diffusion regions 15a, 15b and 150. When it is desired thatthese regions effectively merge into a single heavily-doped P+conductivity-type isolation region 15, as is the case in the presentstructure, the merger may be accomplished by placing the structure ofFIG. 22 in a furnace at a temperature of l200 C. for 12 hours to allowthe P+ conductivity-type regions 15a,

15b and 150 to diffuse together to clearly define the single, deepisolation region 15.

After the formation of deep isolation region 15 (illustrated in FIG. 23)subsequent techniques well-known in the art are utilized to form the Pconductivity-type regions 20 and 21, the P conductivity-typeplanar-diffused base region 23, and the N conductivity-typeplaner-diffused emitter region 24. FIG. 23 illustrates the structureafter these diffusions have been conducted. Note that the final oxidelayer or coating 14 is in place at this point in the processing.

In view of the remarks made previously herein, it will be apparent thatthe structure of FIGS. 1 and 2 is readily prepared from the structure ofFIG. 23.

EXAMPLE The procedure described in connection with preparing thestructure of FIG. 1 was followed in six successive attempts to make thewafer 10 of FIG. 1. The respective substrates used in the efforts werecut with faces at the following maximum angles with the (111) plane: (a)0, (b) -5 minutes, (0) +13 minutes, ((1) 39 minutes, (e) +1.5", (f)-2.75.

The efforts produced visible patterns for the -39 minutes. +1.5", and2.75 faces. The pattern formed on the 39 minutes face was moderatelysharp, sufficiently so to make subsequent fabrication possible. Thepatterns on the 2.75 and +1.5 faces were quite sharp, making subsequentfabrication procedure of quality wafers straightforward. Quite poorpatterns were produced with the substrates having faces cut at 0, 5minutes, and +13 minutes, in fact, so poor that fabrication of the Wafer10 in proper alignment was not possible.

It should be noted that the direction of the angle of misalignment fromthe (111) plane, in accordance with this invention does not appear tomatter. It only appears important that the proper alignment exist.

In accordance with the foregoing description of this invention, it isseen that the invention permits deposition of an epitaxial layer, yetprovides for precise alignment with respect to underlying diffusionregions or other patterns on the substrate. Moreover, it is seen thatsuccessive alignment is provided for a multiplicity of epitaxial layersin which zones or regions of diffusion may be located precisely withrespect to zones or regions in successively formed layers, even thoughthe first formed regions are located in lower layers. Moreover, it isseen that provision is made for forming a deep isolation regionextending through one epitaxial layer, or more, to a substrate by whichindividually formed regions in each may be precisely aligned andconnected by subsequent diffusion to form precisely-aligned, deep,relatively uniformly-doped regions. Such deep regions may be utilized,for example, as isolation zones.

The preferred angle of the face of the substrate with the (111) plane isbetween about 1 and 3 and should not be less than about 0.5" nor greaterthan on the order of about 10.

It has been noted that epitaxial growth on substrate faces cut at asmall angle with the (111) plane has been possible at somewhat lowertemperatures and on somewhat poorer substrates than when the plane onwhich epitaxial deposition is conducted is not inclined a small anglewith the (111) plane. The small critical angle is that referred toabove, i.e. from about 0.5 to on the order of about 10.

The plane of the substrate on which epitaxial deposition is to beconducted may be prepared by a variety of means, e.g. by sawing,lapping, or abrading. Such means of preparation are generically referredto herein as cutting. Accordingly, it is understood that the words cutand cutting are used in the claims hereof in a broad sense, i.e. theseparating and/or removal of material by any effective means whatsoever.7

In the practice of this invention, silicon is preferred as thesemiconductor material of construction for the substrate and overlyingepitaxial layers; however, other semiconductor materials may beemployed. Particularly, the present invention is found most effectivewhen semiconductor materials have cubic crystal structure, such as (butwithout limitation) silicon, germanium, gallium arsenide, and indiumantimonide.

It should be appreciated that the present invention is not limited toforming visible patterns on a substrate by the diffusion-oxide removaltechniques described. Other techniques of visible pattern formation maybe used, for example, etch techniques or selective oxidation techniquesconducted to form a desired, predetermined pattern.

Having described the invention in connection with certain specificembodiments thereof, it is to be understood that further modificationsmay now suggest themselves to those skilled in the art and it isintended to cover such modifications as fall within the scope of theappended claim.

What is claimed is:

1. A monocrystalline wafer for an integrated circuit comprising:

a substrate of substantially monocrystalline semiconductor material ofP-type conductivity,

a first monocrystalline epitaxial layer of N+ conductivity overlyingsaid substrate,

a second monocrystalline epitaxial layer, of N-type conductivity,overlying said first epitaxial layer,

a deep diffusion region of heavily-doped P-type conductivity extendingthrough said first and second epitaxial layers, configured to provideisolation zones of N-type epitaxial material adjacent the surface ofsaid wafer, and

active and passive circuit elements formed in said isolation zonescomprising a pair of NPN transistors with a common collector region anda pair of resistors, said elements being disposed to define a NOR logicnetwork.

References Cited UNITED STATES PATENTS 3,210,677 10/1965 Lin et a1 330173,370,995 2/1968 Lowerm et al. 148175 3,260,902 7/1966 Porter 317-235JERRY D. CRAIG, Examiner US. Cl. X.R. 307-413, 215, 303

